1. Field of the Invention
The invention relates to the manufacture of integrated circuits.
In order to benefit simultaneously from the speed of operation of bipolar transistors, the high density of integration of field effect transistors and the low consumption of circuits using judiciously complementary channel N and channel P field effect transistors, efforts are directed more and more to providing technological manufacturing methods which allow both bipolar transistors and channel N and channel P field effect transistors to be formed on the same integrated circuit substrate.
2. Description of the Prior Art
Unfortunately, the technology of manufacturing field effect transistors is very different from the technology for manufacturing bipolar transistors that does not make the juxtaposition of these two types of transistors on the same substrate impossible but it tends to considerably increase the number of technological steps required for manufacturing these combined circuits; if we start with a CMOS (complementary field effect transistor) technology, bipolar transistors cannot be formed with this technology. Then several technological steps are inserted specific to certain stages of the manufacturing process for forming the desired combined circuits.
Now, the manufacturing steps are already numerous and each additional step tends to reduce, on the one hand, the manufacturing efficiency and, on the other, the possibility of keeping to topological drawing rules corresponding to a high integration density.
Finally, certain usual specific steps in bipolar technologies (N epitaxy on P substrate, formation of localized embedded layers) are long and delicate steps which are fortunately not required in CMOS technologies and which must however be introduced when it is desired to combine CMOS and bipolar technologies on the same substrate.
It will thus be readily understood that this problem of integrating two very different technologies is difficult to solve and that combined CMOS/bipolar circuits have only been able to be constructed to the extent that technological mastery allows an acceptable manufacturing efficiency to be obtained despite the large number of manufacturing steps required.
By way of example, the combined CMOS/bipolar technologies which have been proposed up to present comprise at least 12 different masking levels in their simplest versions.
The present invention provides combined CMOS/bipolar technology which, in its simplest version, only comprises nine masking levels and which further more does not use any epitaxy step nor any formation of localized embedded layer.